Chapter 1IntroductionToday's consumers demand more features, power-efficient devices, and optimized power devices as time goes by. Due to the increasing speed and complexity of designs, there is a significant increase in the power consumption of VLSI chips. Most devices run on battery power rather than electricity. Therefore, optimal battery usage is the most important need. In today's semiconductor designs, lower power consumption is mandatory for mobile and portable applications for longer battery life. Embedded applications are very cost and weight sensitive and don't want to pay for heat sinks and thermal shielding. They are often battery powered and cannot be actively cooled. Therefore, there is a significant need to minimize energy consumption. Power dissipation in CMOS has two components: dynamic power dissipation and static power dissipation. Static power dissipation can be defined as the power dissipated during steady-state conditions or when there is no circuit activity. This is negligible compared to dynamic power dissipation and can be reduced with proper circuit design techniques. Whereas dynamic power dissipation can be defined as the power dissipated under transient state conditions. Each transistor on a chip dissipates a small amount of power when switched, and rapidly switched transistors dissipate more power than slowly switched transistors. Dynamic power dissipation is given by P = C * V2 * fWhere C is the average capacitance of the circuit, V is the supply voltage, and f is the switching frequency or activity. Dynamic power dissipation depends on three factors namely capacitance, voltage and frequency. So reducing these will take effect considering...... middle of paper...... inhibits the clock signal when the idle condition is true and is associated with each sequential functional unit. The clock signal is calculated by the Fclk function. CLK is the system clock and GCLK, the functional unit gated clock. Figure 2.1.1 Principle of clock gating It is an excellent design scheme to turn off the clock when it is not needed. Automatic clock gating is supported by modern EDA tools. They identify circuits where clock gating can be inserted. The RTL phase is the best point in the design process to optimize dynamic power. At this point, the system architecture is defined, the design is clock cycle accurate, and precise power information is available from lower design stages. The only thing left is for hardware designers to have an RTL metric to evaluate and identify candidate logic within a design for clock gating optimization.